1. Field of the Invention
The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor including internal electrodes vertically disposed on a mounting area and having low equivalent series inductance and appropriate equivalent series resistance.
2. Description of the Related Art
Multilayer chip capacitors are generally used as a decoupling capacitor disposed in a high frequency circuit such as a power supply circuit. There are two types of multilayer chip capacitors, such as a multilayer chip capacitor having internal electrodes disposed vertically to a mounting surface and a multilayer chip capacitor having internal electrodes disposed horizontally to a mounting surface. To stabilize a power supply circuit, a multilayer chip capacitor should have a lower equivalent series inductance (ESL) value. This requirement is more increased according to a tendency where high frequency and high current are required in electronic apparatuses. Stability of a power supply circuit depends on an ESL of a multilayer chip capacitor, and particularly, the stability is high at a low ESL. Also, the stability of the power supply circuit depends on not only the ESL of the multilayer chip capacitor but also equivalent series resistance (ESR). When ESR is too small, the power supply circuit lacks stability and a voltage drops sharply. Accordingly, it is important to keep ESR to be suitable.
To reduce ESL, U.S. Pat. No. 5,880,925 discloses a method where leads of a first internal electrode and second internal electrode, which have an opposite polarity to each other, are disposed in an interdigitated arrangement. However, according to the method, since resistances occurring in four leads of the respective internal electrodes are connected to each other in parallel, resistance of an overall capacitor becomes very low. Accordingly, it is difficult to satisfy a target impedance and instability of a power supply circuit is caused.
To prevent ESR from being too low, U.S. Pat. No. 6,441,459 discloses a method where only one lead is used in one internal electrode. However, according to the method, in a boundary area between blocks of internal electrode patterns, directions of currents flowing through mutually adjacent internal electrodes are identical to each other. Accordingly, magnetic flux is not canceled between the adjacent internal electrodes and ESL becomes high.
FIGS. 1A and 1B are perspective views illustrating conventional multilayer chip capacitors. Referring to FIG. 1A, a capacitor 10 includes a capacitor body 11 formed of a lamination of a plurality of dielectric layers 11A and 11B and external electrodes 31 to 34 (shown in dotted lines) formed on a mounting surface A of the capacitor body 11. In FIG. 1A, to show the mounting surface A that is a bottom surface, the capacitor 10 is turned upside down. In the capacitor body 11, internal electrodes 12 and 13 are alternately disposed interposing the dielectric layers 11A and 11B therebetween. The respective internal electrodes 12 and 13 have two leads (16 and 18) and (17 and 19) connected to the external electrodes (31 and 33) and (32 and 34), respectively.
Referring to FIG. 1B, a capacitor 20 includes a capacitor body 21 and external electrodes 3a, 3b, 3c, and 3d formed on a top surface and bottom surface thereof. First and second internal electrodes 22 and 23 having a different polarity from each other have four leads (1b, 1c, 1d, and 1e) and (1b′, 1c′, 1d′, and 1e′) extended to the top surface and bottom surface, respectively.
According to the capacitors 10 and 20 of FIGS. 1A and 1B, since the leads having a different polarity from each other are adjacently disposed to each other, magnetic fluxes caused by currents flowing through the leads are mutually canceled, thereby reducing ESL. However, since a large number of the leads are connected in parallel, ESR becomes excessively low. Particularly, in the capacitor 20, since an effect of reducing ESL is high but ESR becomes excessively low, it is difficult to embody a stable high frequency power supply circuit in decoupling applications.